Alex YD Park, Ph.D.
Hanyang University, Seoul, Korea BS Electrical Engineering, 1988
University of Southern California MS Electrical Engineering, 1997
University of Southern California Ph.D. Electrical Engineering,1999
Alex Yoon Dong Park is a solid-state device architecture and engineer, and his career has included academic and government research, and new technology development leadership. He has over 25 years of experience in the fields of R&D in Semiconductor Device Architecture. He held the position of Vice President, Samsung Advanced Technology Institute(SAIT), Samsung Semiconductor R&D center in Hwasung, South Korea.
In this role, he was responsible for developing the next generation semiconductor devices including 3D NAND flash memory, Vertical Transfer Gate Image sensor, 3D ToF sensor, micro optical spectrometer for mobile PoC biosensor, optical interconnect for DRAM interface. He received the Proud Samsung Award ,Technology Award (Vertical Structure NAND Flash Memory) and Korean Government scholarship.
Dr. Park has published over 50 technical papers and holds over 140 US patents. He worked in Myung-Shin & Partners(~1988), NITI in Korea(~ 2000), NEC in Santa Clara(~2002), and YParkPatent in Palo Alto(~2003). He is a member of AIPLA, Austin IPLA, Houston IPLA Member and senior member of IEEE Circuit and System Society. Dr. Park is a senior associate of the firm.
U.S. Patent and Trademark Office (2003)
- “A 1.5Mpixel RGBZ CMOS image sensor for simultaneous color and range image capture.”ISSCC 2012
- Brain-Implantable Biomimetic Electronics as the Next Era in Neural Prosthetics”, IEEE Proc. VOL. 89, NO7, July 2001
- "A unified submicrometer MOS transistor Charge/ Capacitance Model for Mixed signal IC's'',IEEE Journal of Solid State Circuits, vol.34, pp. 103-106, Jan. 1999.
- "Rheo-optical measurements on suspensions of magnetic recording particles" , J. Appl. Phys., 75(10), pp.5579 (1994).
- "Atomic-layer deposited IrO2 nanodots for charge-trap flash-memory devices", JOURNAL OF PHYSICS D-APPLIED PHYSICS 2007-03-07
- "High trap density and long retention time from self-assembled amorphous Si nanocluster floating gate non-volatile memory" , APPLIED PHYSICS LETTERS 2006-12-14
- “Dual-bit Gate-Sidewall Storage FinFET Non-Volatile Memory Cell and New Method of Charge Detection,” IEEE Electron Device Letters June, 2007 Vol28. No6.
- "Polarity- Dependent Morphological Chabge of Ti/TiN/W Via Under High Current Density". Electron Device Letter. Feb 2010 Vol 31, No2.
- "An Efficient Parameter Extraction Method using Statistical Optimization in S-CMOS Deep- Submicron/Nanometer Model'' ISCAS 2002 IEEE International Symposium on Circuits and System.
- "An Efficient MOS Transistor Charge/ Capacitance Model with Continuous Expressions for VLSI" ISCAS '98.
- "VLSI Implementation of A Dynamic Synaptic Neural Network" Society for Neuroscience 1999 Annual Meeting, Miami Beach, FL.
- "Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses”, IJCNN 2000, Como, Italy.
- Triple high-K stacks (Al2O3/HfO2/Al2O3) with high pressure (10atm) H2 and D2 annealing for SONOS type flash memory device applications IEEE nanoconference 2004-08-17
- “Excellent Resistance Switching Characteristics of Pt/SrTiO3 Schottky Junction for Multi-bit Nonvolatile Memory Application” IEDM 2005-12
- “Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage” VLSI Symposium 2006
- “Multi-bit FinFET Flash Memory Cell Designs and Novel Method of Charge Detection” IEDM 2006-12
- "Architectural Innovation for nanoelectronic devices", Nano Korea 2008
- “Perspective 3D ToF Sensor SOC Integration for User Interface Application” ISOCC2012
- “Mach-Zehnder silicon modulator on bulk silicon substrate; toward DRAM optical interface” Group IV Photonics 2011
- “Bulk silicon photonic wire for one-chip integrated optical interconnection” Group IV Photonics 2011
- “ 10Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface
- Optical interface platform for DRAM integration”
- “10Gb/s, 1x4 optical link for DRAM interconnection” Group IV Photonics 2011
- “Si-based optical I/O for optical memory interface” Photonics West 2012
- “Integration of silicon photonics into DRAM process”
- Atomic-layer deposited IrO2 nanodots for charge-trap flash-memory devices JOURNAL OF PHYSICS D-APPLIED PHYSICS 2007-03-07
- Dual-bit Gate-Sidewall Storage FinFET Non-Volatile Memory Cell and New Method of Charge Detection IEEE Electron Device Letters June, 2007 Vol28. No6.
- Polarity- Dependent Morphological Chabge of Ti/TiN/W Via Under High Current Density Electron Device Letter. Feb 2010 Vol 31, No2.
- “Dark Current Suppression during High Speed Photogate Modulation for 3D ToF Imaging Pixel” International image sensor workshop, 2011,
- “Si Photonic DRAM Process Integration OFC/NFOEC : Optical Fiber Communication Conference and Exposition and National Fiber Optic Engineers Conference
- “Perspectives on 3D ToF Sensor SoC Integration for User Interface Application”ISOCC(International SoC Design Conference
- Stochastic Performance Simulation of Three-Dimensional Time-of-Flight CMOS Image Sensor: Perspectives for Pixel Miniaturization Applied Optics
- Multiple 3D ToF camera Modulation SPIE Electronic Imaging
- RGBZ sensor Demosaic Algorithm SPIE Electronic Imaging
- A 1.5Mpixel RGBZ CMOS Image Sensor for User Interface and 3D Image Capture IDW : SID International Display Workshops
- Dark Current Suppression during High Speed Photogate Modulation for 3D ToF Imaging Pixel International Image Sensor Workshop (IISW) 2011
- A 192X108 pixel ToF-3D image sensor with a single-tap concentric-gate demodulation pixels in 0.13 um technology, IEEE International Electron Devices Meeting (2011 IEDM)
- DRAM interconnect 10Gbps, 1x4 Optical Link, IEEE Photonics Society 2013: Group IV Photonics
- A Time-of-Flight 3-D Image Sensor With Concentric-Photogates Demodulation Pixels Electron Devices, IEEE Transactions on, vol 61 , p870 March 2014.
- Bulk-Si photonics technology for DRAM interface [Invited] Byun et al. Vol. 2, No. 3 / June 2014 / Photon. Res. A25